Artificial Intelligence

Hardware Research

MARS: Multi-macro Architecture SRAM CIMBased Accelerator with Co-designed Compressed Neural Networks

 Convolutional neural networks (CNNs) play a key role in deep learning applications. However, the large storage overheads and the substantial computational cost of CNNs are problematic in hardware accelerators. Computing-inmemory (CIM) architecture has demonstrated great potential to effectively compute large-scale matrix–vector multiplication. However, the intensive multiply and accumulation (MAC) operations executed on CIM macros remain bottlenecks for further improvement of energy efficiency and throughput. To reduce computational costs, ......

Algorithm Research

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array

 Recent advances in neuromorphic computing system have shown resistive random-access memory (ReRAM) can be used to efficiently implement compact parallel computing arrays, which are inherently suitable for neural networks that require large amounts of matrix-vector multiplications (MVMs). In this work, we proposed a neuromorphic computing system based on ReRAM synaptic array to implement bitwise neural networks. The system contains a ReRAM synaptic array for parallel computation of bitwise MVMs, and a field-programmable gate array for data buffering and processing ......

System Research

Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices

 In quest to execute emerging deep learning algorithms at edge devices, developing low-power and low-latency deep learning accelerators (DLAs) have become top priority. To achieve this goal, data processing techniques in sensor and memory utilizing the array structure have drawn much attention. Processing-in-sensor (PIS) solutions could reduce data transfer; computing-in-memory (CIM) macros could reduce memory access and intermediate data movement. We propose a new architecture to integrate PIS and CIM to realize low-power DLA. The advantages of using these techniques and the challenges from system point-of-view are discussed......

Demo Video - 1

CIM-Based Accelerator Chip

Demo Video - 2

CIM-Based Accelerator Moving Object Detection